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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
February 2006
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Features
5V tolerant inputs and outputs 2.3V-3.6V VCC specifications provided 8.0ns tPD max (VCC = 3.3V), 10A ICC max Power down high impedance inputs and outputs Supports live insertion/withdrawal1 24mA output drive (VCC = 3.0V) Implements patented noise/EMI reduction circuitry Latch-up performance exceeds JEDEC 78 conditions ESD performance
General Description
The LCX373 consists of eight latches with 3-STATE outputs for bus organized system applications. The device is designed for low voltage applications with capability of interfacing to a 5V signal environment. The LCX373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
- Human body model > 2000V - Machine model > 200V Leadless Pb-Free DQFN package
Ordering Information
Order Number
74LCX373WM 74LCX373SJ 74LCX373BQX2 74LCX373MSA 74LCX373MTC 74LCX373MTCX_NL3
Package Number
M20B M20D MLP020B MSA20 MTC20 MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Notes: 1. To ensure the high impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. 2. DQFN package available in Tape and Reel only. 3. "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
(c)2006 Fairchild Semiconductor Corporation
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74LCX373 Rev. 2.0.0
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Logic Symbols
D0 D1 D2 D3 D4 D5 D6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 IEEE/IEC OE LE D0 D1 D2 D3 D4 D5 D6 D7 EN C1 1D O0 O1 O2 O3 O4 O5 O6 O7
Pin Descriptions
Pin Names
D0-D7 LE OE O0-O7 Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs
Description
Truth Table
Inputs LE
X H H L
Outputs Dn
X L H X
OE
H L L L
On
Z L H O0
Connection Diagrams
Pin Assignments for SOIC, SOP, SSOP, TSSOP
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
Functional Description
The LCX373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Pad Assignments for DQFN
OE VCC
1 20 19 18 17 16 15 14 13 12 10 11
O0 2 D0 3 D1 4 O1 5 O2 6 D2 7 D3 8 O3 9 GND LE
O7 D7 D6 O6 O5 D5 D4 O4
(Top View)
2 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Logic Diagram
D0 D O D1 D O D2 D O D3 D O D4 D O D5 D O D6 D O D7 D O
G LE
G
G
G
G
G
G
G
OE O0 O1 O2 O3 O4 O5 O6 O7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Absolute Maximum Ratings
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Symbol
VCC VI VO IIK IOK IO ICC IGND TSTG
Parameter
Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature
Conditions
Value
-0.5 to +7.0 -0.5 to +7.0
Units
V V V mA mA mA mA mA C
Output in 3-STATE Output in HIGH or LOW VI < GND VO < GND VO > VCC State4
-0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150
Recommended Operating Conditions5
Symbol
VCC VI VO IOH / IOL
Parameter
Supply Voltage Input Voltage Output Voltage Output Current
Conditions
Operating Data Retention HIGH or LOW State 3-STATE VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V VCC = 2.3V - 2.7V
Min.
2.0 1.5 0 0 0
Max.
3.6 3.6 5.5 VCC 5.5 24 12 8
Units
V V V mA
TA t / V
Free-Air Operating Temperature Input Edge Rate VIN = 0.8V - 2.0V, VCC = 3.0V
-40 0
85 10
C ns /V
Notes: 4. IO Absolute Maximum Rating must be observed. 5. Unused inputs must be held HIGH or LOW. They may not float.
4 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
DC Electrical Characteristics
TA = -40C to +85C Symbol
VIH VIL VOH
Parameter
HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage
Conditions
VCC (V)
2.3 - 2.7 2.7 - 3.6 2.3 - 2.7 2.7 - 3.6
Min.
1.7 2.0
Max.
Units
V
0.7 0.8 VCC - 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 5.0 5.0 10 10 10 500
V V
IOH = -100 A IOH = -8 mA IOH = -12 mA IOH = -18 mA IOH = -24 mA
2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 - 3.6 0 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6 5.5V6
VOL
LOW Level Output Voltage
IOL = 100 A IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA
V
II IOZ IOFF ICC ICC
Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current Quiescent Supply Current Increase in ICC per Input
0 VI 5.5V 0 VO 5.5V, VI = VIH or VIL VI or VO = 5.5V VI = VCC or GND 3.6V VI, VO VIH = VCC -0.6V
A A A A A
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 VCC = 3.3V 0.3V CL = 50pF Symbol
tPHL, tPLH tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tS tH tW
VCC = 2.7V CL = 50pF Min.
1.5 1.5 1.5 1.5 2.5 1.5 3.3
VCC = 2.5 0.2V CL = 30pF Min.
1.5 1.5 1.5 1.5 4.0 2.0 4.0
Parameter
Propagation Delay, Dn to On Propagation Delay, LE to On Output Enable Time Output Disable Time Setup Time, Dn to LE Hold Time, Dn to LE LE Pulse Width Skew7
Min.
1.5 1.5 1.5 1.5 2.5 1.5 3.3
Max.
8.0 8.5 8.5 7.5
Max.
9.0 9.5 9.5 8.5
Max.
9.6 10.5 10.5 9.0
Units
ns ns ns ns ns ns ns ns
tOSHL, tOSLH Output to Output
1.0
Notes: 6. Outputs disabled or 3-STATE only. 7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL) or LOW-to-HIGH (tOSLH).
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Dynamic Switching Characteristics
TA = 25C Symbol
VOLP VOLV
Parameter
Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL
Conditions
CL = 50pF, VIH = 3.3V, VIL = 0V CL = 30pF, VI = 2.5V, VIL = 0V CL = 50pF, VIH = 3.3V, VIL = 0V CL = 30pF, VI = 2.5V, VIL = 0V
VCC (V)
3.3 2.5 3.3 2.5
Typical
0.8 0.6 -0.8 -0.6
Units
V V
Capacitance
Symbol
CIN COUT CPD
Parameter
Input Capacitance Output Capacitance Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10MHz
Typical
7 8 25
Units
pF pF pF
6 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
AC Loading and Waveforms (Generic for LCX Family)
VCC TEST SIGNAL 500
DUT
OPEN GND VI
tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
CL
500
Figure 1. AC Test Circuit (CL includes probe and jig capacitance) Test
tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
Switch
Open 6V at VCC = 3.3 0.3V VCC x 2 at VCC = 2.5 0.2V GND
DATA IN tpxx DATA OUT
Vmi tpxx Vmo
VCC GND
OUTPUT CONTROL tPZH DATA OUT Vmo tPHZ
Vmi
VCC GND VOH VY
Waveform for Inverting and Non-Inverting Functions
tW CONTROL IN Vmi trec CLOCK tPHL OUTPUT Vmo Vmi tPLH Vmo VCC GND
3-STATE Output High Enable and Disable Times for Logic
DATA IN tS CONTROL INPUT tS MR OR CLEAR trec Vmi tH Vmi Vmi VCC GND VCC GND
Propagation Delay, Pulse Width and trec Waveforms
OUTPUT CONTROL tPZL DATA OUT Vmo tPLZ Vmi VCC GND VX VOL ANY OUTPUT
Setup Time, Hold Time and Recovery Time for Logic
tr tf VOH VOL
90% 10%
90% 10%
3-STATE Output Low Enable and Disable Times for Logic
trise and tfall
Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns) VCC Symbol
Vmi Vmo Vx Vy
3.3V 0.3V
1.5V 1.5V VOL + 0.3V VOH - 0.3V
7
2.7V
1.5V 1.5V VOL + 0.3V VOH - 0.3V
2.5V 0.2V
VCC / 2 VCC / 2 VOL + 0.15V VOH - 0.15V
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74LCX373 Rev. 2.0.0
74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Schematic Diagram (Generic for LCX Family)
Input Stage
P2 P1 VCC
Data ESD D2 N+/P- N1 N2 GTOTM Input Stage P4 D6 N+/P- P5 X1 VDD
Output
P3 N5 Enable ESD D4 N+/P- N3
N4
8 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Tape and Reel Specification
Tape Format for DQFN Package Designator
BQX
Tape Section
Leader (Start End) Carrier Trailer (Hub End)
Number Cavities
125 (typ) 3000 75 (typ)
Cavity Status
Empty Filled Empty
Cover Tape Status
Sealed Sealed Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
12 mm
A
13.0 (330.0)
B
0.059 (1.50)
C
0.512 (13.00)
D
0.795 (20.20)
N
2.165 (55.00)
W1
0.488 (12.4)
W2
0.724 (18.4)
9 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
10 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
11 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package Number MLP020B
12 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
13 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
Physical Dimensions (Continued) inches (millimeters) unless otherwise noted
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
14 74LCX373 Rev. 2.0.0
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74LCX373 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILDiS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I18
15 74LCX373 Rev. 2.0.0
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